STM32F107VC/GPIO - Revision history

Heth: /* MODE[1:0] configuratin bits */

2011-11-15T07:17:28Z

‎MODE[1:0] configuratin bits

Heth: /* GPIO Configuration Registers summary */

2011-09-01T11:55:46Z

‎GPIO Configuration Registers summary

Heth: /* GPIO Configuration Registers summary */

2011-08-28T09:23:57Z

‎GPIO Configuration Registers summary

Heth: /* Port Bit Configuration */

2011-08-28T09:23:07Z

‎Port Bit Configuration

Heth at 09:20, 28 August 2011

2011-08-28T09:20:10Z

Heth: /* Port Bit Configuration */

2011-08-28T09:18:38Z

‎Port Bit Configuration

Heth: /* Port Bit Configuration */

2011-08-28T08:44:58Z

‎Port Bit Configuration

Heth: /* Port Bit Configuration */

2011-08-28T08:13:30Z

‎Port Bit Configuration

Heth: /* Detailed description */

2011-08-28T07:59:39Z

‎Detailed description

Heth: /* Port Bit Configuration */

2011-08-28T07:58:56Z

‎Port Bit Configuration

@@ Line 66: / Line 66: @@
 |-
 |}
-====MODE[1:0] configuratin bits====
+====MODE[1:0] configuration bits====
 {|border=1 ;style="margin: 0 auto; text-align: center;cellpadding="5" cellspacing="0"
 |+ Output MODE bits.

@@ Line 28: / Line 28: @@
 ! Name  !! [http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00171190.pdf Section] !! Name || r/w || Bits ||Function
 |-
-|[[/GPIO''x''_CRL|GPIO'''x'''_CRL]] || align=center | 9.2.1 || Port configuration register low || align=center | rw || CNF[1:0], MODE[1:0] ||Configure lowest 8 bit of port ''x''. IN or OUT
+|[[/GPIOx_CRL|GPIO'''x'''_CRL]] || align=center | 9.2.1 || Port configuration register low || align=center | rw || CNF[1:0], MODE[1:0] ||Configure lowest 8 bit of port ''x''. IN or OUT
 |-
-|[[/GPIO''x''_CRH|GPIO'''x'''_CRH]] || align=center | 9.2.2 || Port configuration register high || align=center | rw ||CNF[1:0], MODE[1:0] ||Configure highest 8 bit of port ''x''. IN or OUT
+|[[/GPIOx_CRH|GPIO'''x'''_CRH]] || align=center | 9.2.2 || Port configuration register high || align=center | rw ||CNF[1:0], MODE[1:0] ||Configure highest 8 bit of port ''x''. IN or OUT
 |-
-|[[/GPIO''x''_IDR|GPIO'''x'''_IDR]] || align=center | 9.2.3 || port input data register || align=center | r ||IDR[15:0] ||Read state of pins configured for input on port ''x'' (Lowest 16 bits of word)
+|[[/GPIOx_IDR|GPIO'''x'''_IDR]] || align=center | 9.2.3 || port input data register || align=center | r ||IDR[15:0] ||Read state of pins configured for input on port ''x'' (Lowest 16 bits of word)
 |-
-|[[/GPIO''x''_ODR|GPIO'''x'''_ODR]] || align=center | 9.2.4 || port output data register || align=center | rw || ODR[15:0]||Write to pins configured for Output on port ''x'' (Lowest 16 bits of word)
+|[[/GPIOx_ODR|GPIO'''x'''_ODR]] || align=center | 9.2.4 || port output data register || align=center | rw || ODR[15:0]||Write to pins configured for Output on port ''x'' (Lowest 16 bits of word)
 |-
-|[[/GPIO''x''_BSRR|GPIO'''x'''_BSRR]] || align=center | 9.2.5 || Port bit set/reset register || align=center | w ||BS[15:0], BR[15:0] || Atomic Set/Reset individual Pins configured for Output.
+|[[/GPIOx_BSRR|GPIO'''x'''_BSRR]] || align=center | 9.2.5 || Port bit set/reset register || align=center | w ||BS[15:0], BR[15:0] || Atomic Set/Reset individual Pins configured for Output.
 |-
-|[[/GPIO''x''_BRR|GPIO'''x'''_BRR]] || align=center | 9.2.6 || Port bit reset register || align=center | w ||BR[15:0] || Atomic Reset individual Pins configured for Output. (Lowest 16 bits of word)
+|[[/GPIOx_BRR|GPIO'''x'''_BRR]] || align=center | 9.2.6 || Port bit reset register || align=center | w ||BR[15:0] || Atomic Reset individual Pins configured for Output. (Lowest 16 bits of word)
 |-
-|[[/GPIO''x''_LCKR|GPIO'''x'''_LCKR]] || align=center | 9.2.7 || Port configuration lock register || align=center | rw ||LCK[15:0], LCKK|| Lock individual pins of port ''x'' (Freeze CRL and CRH of ports)
+|[[/GPIOx_LCKR|GPIO'''x'''_LCKR]] || align=center | 9.2.7 || Port configuration lock register || align=center | rw ||LCK[15:0], LCKK|| Lock individual pins of port ''x'' (Freeze CRL and CRH of ports)
 |}

@@ Line 28: / Line 28: @@
 ! Name  !! [http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00171190.pdf Section] !! Name || r/w || Bits ||Function
 |-
-|[[/GPIO''x''_CRL|GPIO'''x'''_CRL]] || align=center | 9.2.1 || Port configuration register low || align=center | rw || CNF[1,0], MODE[1,0] ||Configure lowest 8 bit of port ''x''. IN or OUT
+|[[/GPIO''x''_CRL|GPIO'''x'''_CRL]] || align=center | 9.2.1 || Port configuration register low || align=center | rw || CNF[1:0], MODE[1:0] ||Configure lowest 8 bit of port ''x''. IN or OUT
 |-
-|[[/GPIO''x''_CRH|GPIO'''x'''_CRH]] || align=center | 9.2.2 || Port configuration register high || align=center | rw ||CNF[1,0], MODE[1,0] ||Configure highest 8 bit of port ''x''. IN or OUT
+|[[/GPIO''x''_CRH|GPIO'''x'''_CRH]] || align=center | 9.2.2 || Port configuration register high || align=center | rw ||CNF[1:0], MODE[1:0] ||Configure highest 8 bit of port ''x''. IN or OUT
 |-
 |[[/GPIO''x''_IDR|GPIO'''x'''_IDR]] || align=center | 9.2.3 || port input data register || align=center | r ||IDR[15:0] ||Read state of pins configured for input on port ''x'' (Lowest 16 bits of word)
@@ Line 42: / Line 42: @@
 |[[/GPIO''x''_LCKR|GPIO'''x'''_LCKR]] || align=center | 9.2.7 || Port configuration lock register || align=center | rw ||LCK[15:0], LCKK|| Lock individual pins of port ''x'' (Freeze CRL and CRH of ports)
 |}
 ===Port bit Configuration summary===
 {|border=1 ;style="margin: 0 auto; text-align: center;cellpadding="5" cellspacing="0"

@@ Line 22: / Line 22: @@
 ==Port Bit Configuration==
 Each bit can be configured using the configuration registers shown below
 {|border=1 ;style="margin: 0 auto; text-align: center;cellpadding="5" cellspacing="0" width=100%
 |+ GPIO Configuration Registers. ('''Note:'''''x'' = Port A to G )
@@ Line 41: / Line 42: @@
 |[[/GPIO''x''_LCKR|GPIO'''x'''_LCKR]] || align=center | 9.2.7 || Port configuration lock register || align=center | rw ||LCK[15:0], LCKK|| Lock individual pins of port ''x'' (Freeze CRL and CRH of ports)
 |}
+===Port bit Configuration summary===
 {|border=1 ;style="margin: 0 auto; text-align: center;cellpadding="5" cellspacing="0"
 |+ Port bit configuration table
@@ Line 64: / Line 65: @@
 |-
 |}
 {|border=1 ;style="margin: 0 auto; text-align: center;cellpadding="5" cellspacing="0"
 |+ Output MODE bits.

@@ Line 22: / Line 22: @@
 ==Port Bit Configuration==
 Each bit can be configured using the configuration registers shown below
-{|border=1 ;style="margin: 0 auto; text-align: center;cellpadding="5" cellspacing="0"
+{|border=1 ;style="margin: 0 auto; text-align: center;cellpadding="5" cellspacing="0" width=100%
 |+ GPIO Configuration Registers. ('''Note:'''''x'' = Port A to G )
 |- bgcolor=lightgrey

@@ Line 25: / Line 25: @@
 |+ GPIO Configuration Registers.
 |- bgcolor=lightgrey
-! Name  !! Function
+! Name  !! [http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00171190.pdf Section] !! Function
 |-
-|A ||A
+|[[/GPIO'''x'''_CRL|GPIO'''x'''_CRL]] || align=center | 9.2.1 || Port configuration register low ('''x''' = Port A to G )
 |-
-|B||B
+|[[/GPIO'''x'''_CRH|GPIO'''x'''_CRH]] || align=center | 9.2.2 || Port configuration register high ('''x''' = Port A to G )
 |-
 |}

@@ Line 53: / Line 53: @@
 |- align=center
 |  align=left |Input Pull-Up|| 1
 |-
 |}

@@ Line 57: / Line 57: @@
 ==Detailed description==
-For detailed description see [http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00171190.pdf STM32F107VC Reference Manual] Chapter 9.
+For detailed description of GPIO see [http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00171190.pdf STM32F107VC Reference Manual] Chapter 9.
 [[Category:ARM]]

@@ Line 38: / Line 38: @@
 ! colspan=2 |Configuration mode !! CNF1 !! CNF0 !! MODE1 !! MODE0 !! PxODR register
 |- align=center
-|rowspan=2 align=left|General Purpose Output || align=left |Push-Pull||rowspan=2; |0||0||rowspan=4; colspan=2|00<br/>01<br/>10<br/>|| 0 or 1
+|rowspan=2 align=left|General Purpose Output || align=left |Push-Pull||rowspan=2; |0||0||rowspan=4; colspan=2|01<br/>10<br/>11<br/>See Mode below|| 0 or 1
 |- align=center
 | align=left |Open Drain ||1|| 0 or 1
 |- align=center
-|rowspan=2 align=left |Alternate function Output || align=left |Push-Pull||rowspan=2; |1||0|| Dont Care
+|rowspan=2 align=left |Alternate function Output || align=left |Push-Pull||rowspan=2; |1||0|| Don't Care
 |- align=center
-| align=left |Open Drain ||1|| Dont Care
+| align=left |Open Drain ||1|| Don't Care
 |- align=center
-|rowspan=4 align=left |Input || align=left |Analog||rowspan=2; |0||0||rowspan=4; colspan=2|00|| Dont Care
+|rowspan=4 align=left |Input || align=left |Analog||rowspan=2; |0||0||rowspan=4; colspan=2|00|| Don't Care
 |- align=center
-|  align=left |Input Floating|| 1 || Dont Care
+|  align=left |Input Floating|| 1 || Don't Care
 |- align=center
 |  align=left |Input Pull-Down|| rowspan=2 | 1 || rowspan=2 | 0 || 0