STM32F107VC/RCC - Revision history

Heth at 05:57, 26 January 2012

2012-01-26T05:57:32Z

Heth: moved STM32F107VC/RSS to STM32F107VC/RCC: Wrong name

2012-01-26T05:57:16Z

moved STM32F107VC/RSS to STM32F107VC/RCC: Wrong name

Heth: /* RCC - reset and clock control */

2011-09-23T09:55:45Z

‎RCC - reset and clock control

Heth: /* PLL - Phase Locked Loops */

2011-09-19T11:14:08Z

‎PLL - Phase Locked Loops

Heth: /* Clock Paths */

2011-09-11T11:53:20Z

‎Clock Paths

Heth: /* Reset */

2011-09-06T06:00:06Z

‎Reset

Heth: /* PLL - Phase Locked Loops */

2011-09-06T05:02:03Z

‎PLL - Phase Locked Loops

Heth: /* Clocks */

2011-09-06T04:50:27Z

‎Clocks

Heth at 12:06, 1 September 2011

2011-09-01T12:06:23Z

Heth: Created page with "=RCC - reset and clock control = Clock Tree (Click to enlarge) STM32F107VC is a Connectivity Line Device and this register refe..."

2011-08-31T11:46:50Z

Created page with "=RCC - reset and clock control = right|thumb|300px|Clock Tree (Click to enlarge) STM32F107VC is a Connectivity Line Device and this register refe..."

New page

=RCC - reset and clock control =
[[Image:ARM clock tree.png|right|thumb|300px|Clock Tree (Click to enlarge)]]
[[STM32F107VC]] is a Connectivity Line Device and this register refers to Chapter 8 in [http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00171190.pdf The Reference manual].
==Reset==
There are three tyoes of reset
#System Reset
#Power Reset
#Backup Domain Reset
===System Reset===

__NOTOC__
[[Category:ARM]]

@@ Line 1: / Line 1: @@
-=RCC - reset and clock control =
+=RSS - reset and clock control =
 [[Image:ARM clock tree.png|right|thumb|300px|Clock Tree (Click to enlarge)]]
 [[STM32F107VC]] is a Connectivity Line Device and this register refers to Chapter 8 in [http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00171190.pdf The Reference manual].
@@ Line 40: / Line 40: @@
 *HSI clock divided by 2
 *HSE or PLL2 clock through a configurable divider
 =Example=
 *[http://mars.tekkom.dk/data/startup%20clock.zip Clock mode 1 and clock mode 5 example]
 __NOTOC__
 [[Category:STM32F107VC]][[Category:ARM]]

@@ Line 40: / Line 40: @@
 *HSI clock divided by 2
 *HSE or PLL2 clock through a configurable divider
+=Example=
 __NOTOC__
 [[Category:STM32F107VC]][[Category:ARM]]

@@ Line 14: / Line 14: @@
 *HSE oscillator clock
 *PLL clock
-===Clock Paths===
+===Clock Modes===
 *The SYSCLK and Cortex M3 Clock can be configured in five different paths. See [[/Clock Paths|Clock Paths]]
 ===HSI - High Speed Internal Clock===
 The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used

← Older revision		Revision as of 05:02, 6 September 2011
Line 39:		Line 39:

	__NOTOC__		__NOTOC__
−	[[Category:ARM]]	+	[[Category:STM32F107VC]][[Category:ARM]]

@@ Line 13: / Line 13: @@
 *HSE oscillator clock
 *PLL clock
 ===HSI - High Speed Internal Clock===
 The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used

← Older revision	Revision as of 05:57, 26 January 2012
(No difference)

@@ Line 3: / Line 3: @@
 [[STM32F107VC]] is a Connectivity Line Device and this register refers to Chapter 8 in [http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00171190.pdf The Reference manual].
 ==Reset==
-There are three tyoes of reset
+There are three types of reset
 #System Reset
 #Power Reset
 #Backup Domain Reset
 Se section 8.1 of the [http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00171190.pdf The Reference manual] for further information.
 ==Clocks==
 Three different clock sources can be used to drive the system clock (SYSCLK):