Difference between revisions of "STM32F107VC/Using the RTC Real Time Clock"
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[[category:STM32F107VC]][[Category:ARM]]  | [[category:STM32F107VC]][[Category:ARM]]  | ||
Revision as of 14:51, 6 March 2012
Preparing for programming the STM32F107VC Real Time Clock.
//Define where in the memory the RTC start address peripheral is located
#define RTC_BASE         0x40002800 // See reference manual page 52
//Define the RTC register map. See reference manual section 18.4.7 page 474
unsigned short int volatile * const rtc_crh  = (unsigned short int *) RTC_BASE + 0x0;
unsigned short int volatile * const rtc_crl  = (unsigned short int *) RTC_BASE + 0x4;
unsigned short int volatile * const rtc_prlh = (unsigned short int *) RTC_BASE + 0x8;
//Initialize the RTC peripheral. See reference manual section 18 page 463
void rtc_init(void) {
 // Your code here
}
Initializing the RTC
- Goals
 - Enabling the RTC
 - One seconds TICK
 - No interrupts enable
 - Initializing second counter to present time (Epoch 1/1-1970 00:00:00)
 - Using external XTAL
 - Write protect against accidental writes
 
Enabling the RTC
- To enable the RTC it is necessary to enable the Power interface in the RCC->APB1ENR register by setting the PWREN bit to 1. [1]
 - To disable write protection to the Backup domain control register - enabling configuration of the RTC in the PWR->CR register setting the DBP bit to 1. [2]
 - To select LSE (Low Speed External XTAL) as clocksource in the RCC->BDCR register bits RTCSEL[1:0] = 01 [3]
 - To turn on the LSE in the RCC->BDCR register bit LSEON = 1.[4]
 - Wait in while loop (timed out for error check) for the LSE to be ready in RCC->BDCR register bit LSERDY.[5]
 - Setting the prescaler of the RTC counter - assuming a 32,768 KHz XTAL - in register RTC->PRLH = 0 and RTC->PRLL = 0x7fff.[6]
 - Setting the Counter to the current time in seconds since epoch. (Set the RTC->CNTH before the RTC->CNTL avoiding RTC->CNTL = 0xffff incrementing RTC->CNTH before writing to it.) [7]
 - To enable write protection to the Backup domain control register - disableing configuration of the RTC in the PWR->CR register setting the DBP bit to 0. [8]
 
Links
References
- ↑ Reference manual section 8.3.8 page 144
 - ↑ Reference manual section 5.4.1 page 75
 - ↑ Reference manual section 8.3.9 page 146
 - ↑ Reference manual section 8.3.9 page 146
 - ↑ Reference manual section 8.3.9 page 146
 - ↑ Reference manual section 18.4.3 page 470
 - ↑ Reference manual section 18.4.5 page 472
 - ↑ Reference manual section 5.4.1 page 75