Difference between revisions of "STM32F107VC/Using the RTC Real Time Clock"

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m (→‎Enabling the RTC)
m (→‎Enabling the RTC)
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:Using external XTAL
 
:Using external XTAL
 
:Write protect against accidental writes
 
:Write protect against accidental writes
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==Enabling the RTC==
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== Enabling the RTC ==
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+
===Power on Init===
−
#To enable the RTC it is necessary to enable the Power interface in the RCC->APB1ENR register by setting the PWREN bit to 1. <ref>Reference manual section 8.3.8 page 144</ref>
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#To enable the RTC it is necessary to enable the Power interface in the RCC-&gt;APB1ENR register by setting the PWREN bit to 1. <ref>Reference manual section 8.3.8 page 144</ref>  
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#To select the voltage threshold when the RTC switch to battery power. E2PROM minimum operating voltage is 2.5 V. In the PWR->CR register set PLS[2:0] to 011<ref>Reference manual section 5.4.1 page 75</ref>
+
#To select the voltage threshold when the RTC switch to battery power. E2PROM minimum operating voltage is 2.5 V. In the PWR->CR register set PLS[2:0] to 011<ref name="CR">Reference manual section 5.4.1 page 75</ref>  
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#To enable the ''Power voltage detector'' in the PWR->CR register set PVDE to 1.<ref>Reference manual section 5.4.1 page 75</ref>
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#To enable the ''Power voltage detector'' in the PWR-&gt;CR register set PVDE to 1.<ref>Reference manual section 5.4.1 page 75</ref>  
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#To disable write protection to the Backup domain control register - enabling configuration of the RTC in the PWR->CR register setting the DBP bit to 1. <ref>Reference manual section 5.4.1 page 75</ref>
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===Checking if RTC running===
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#To select LSE (Low Speed External XTAL) as clocksource in the RCC->BDCR register bits RTCSEL[1:0] = 01 <ref>Reference manual section 8.3.9 page 146</ref>
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#In the RCC->BDCR Register check if the RTCEN bit is 1 and the LSEON is 1 and LSERDY is 1 - If not the RTC is not running and need programming. (See below)<ref name="BDCR">Reference manual section 8.3.9 page 146</ref>
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#To turn on the LSE in the RCC->BDCR register bit LSEON = 1.<ref>Reference manual section 8.3.9 page 146</ref>
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===Programming the RTC===
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#Wait in while loop (timed out for error check) for the LSE to be ready in RCC->BDCR register bit LSERDY.<ref>Reference manual section 8.3.9 page 146</ref>
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#To disable write protection to the Backup domain control register - enabling configuration of the RTC in the PWR-&gt;CR register setting the DBP bit to 1. <ref name="CR"></ref>  
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#Setting the prescaler of the RTC counter - assuming a 32,768 KHz XTAL - in register RTC->PRLH = 0 and RTC->PRLL = 0x7fff.<ref> Reference manual section  18.4.3 page 470</ref>
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#To select LSE (Low Speed External XTAL) as clocksource in the RCC-&gt;BDCR register bits RTCSEL[1:0] = 01 <ref name=BDCR>Reference manual section 8.3.9 page 146</ref>  
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#Setting the Counter to the current time in seconds since epoch. (Set the RTC->CNTH before the RTC->CNTL avoiding RTC->CNTL = 0xffff incrementing RTC->CNTH before writing to it.) <ref>Reference manual section 18.4.5 page 472</ref>
+
#To turn on the LSE in the RCC-&gt;BDCR register bit LSEON = 1.<ref>Reference manual section 8.3.9 page 146</ref>  
−
#To enable write protection to the Backup domain control register - disableing configuration of the RTC in the PWR->CR register setting the DBP bit to 0. <ref>Reference manual section 5.4.1 page 75</ref>
+
#Wait in while loop (timed out for error check) for the LSE to be ready in RCC-&gt;BDCR register bit LSERDY.<ref>Reference manual section 8.3.9 page 146</ref>  
 +
#Setting the prescaler of the RTC counter - assuming a 32,768 KHz XTAL - in register RTC-&gt;PRLH = 0 and RTC-&gt;PRLL = 0x7fff.<ref> Reference manual section  18.4.3 page 470</ref>  
 +
#Setting the Counter to the current time in seconds since epoch. (Set the RTC-&gt;CNTH before the RTC-&gt;CNTL avoiding RTC-&gt;CNTL = 0xffff incrementing RTC-&gt;CNTH before writing to it.) <ref>Reference manual section 18.4.5 page 472</ref>  
 +
#To enable write protection to the Backup domain control register - disableing configuration of the RTC in the PWR-&gt;CR register setting the DBP bit to 0. <ref>Reference manual section 5.4.1 page 75</ref>
  
 
=Links=
 
=Links=

Revision as of 08:26, 7 March 2012

Preparing for programming the STM32F107VC Real Time Clock. 

//Define where in the memory the RTC start address peripheral is located
#define RTC_BASE         0x40002800 // See reference manual page 52

//Define the RTC register map. See reference manual section 18.4.7 page 474
unsigned short int volatile * const rtc_crh  = (unsigned short int *) RTC_BASE + 0x0;
unsigned short int volatile * const rtc_crl  = (unsigned short int *) RTC_BASE + 0x4;
unsigned short int volatile * const rtc_prlh = (unsigned short int *) RTC_BASE + 0x8;

//Initialize the RTC peripheral. See reference manual section 18 page 463
void rtc_init(void) {
 // Your code here
}

Initializing the RTC

Goals
Enabling the RTC
One seconds TICK
No interrupts enable
Initializing second counter to present time (Epoch 1/1-1970 00:00:00)
Using external XTAL
Write protect against accidental writes

Enabling the RTC

Power on Init

  1. To enable the RTC it is necessary to enable the Power interface in the RCC->APB1ENR register by setting the PWREN bit to 1. [1]
  2. To select the voltage threshold when the RTC switch to battery power. E2PROM minimum operating voltage is 2.5 V. In the PWR->CR register set PLS[2:0] to 011[2]
  3. To enable the Power voltage detector in the PWR->CR register set PVDE to 1.[3]

Checking if RTC running

  1. In the RCC->BDCR Register check if the RTCEN bit is 1 and the LSEON is 1 and LSERDY is 1 - If not the RTC is not running and need programming. (See below)[4]

Programming the RTC

  1. To disable write protection to the Backup domain control register - enabling configuration of the RTC in the PWR->CR register setting the DBP bit to 1. [2]
  2. To select LSE (Low Speed External XTAL) as clocksource in the RCC->BDCR register bits RTCSEL[1:0] = 01 [4]
  3. To turn on the LSE in the RCC->BDCR register bit LSEON = 1.[5]
  4. Wait in while loop (timed out for error check) for the LSE to be ready in RCC->BDCR register bit LSERDY.[6]
  5. Setting the prescaler of the RTC counter - assuming a 32,768 KHz XTAL - in register RTC->PRLH = 0 and RTC->PRLL = 0x7fff.[7]
  6. Setting the Counter to the current time in seconds since epoch. (Set the RTC->CNTH before the RTC->CNTL avoiding RTC->CNTL = 0xffff incrementing RTC->CNTH before writing to it.) [8]
  7. To enable write protection to the Backup domain control register - disableing configuration of the RTC in the PWR->CR register setting the DBP bit to 0. [9]

Links

References

  1. ↑ Reference manual section 8.3.8 page 144
  2. ↑ 2.0 2.1 Reference manual section 5.4.1 page 75
  3. ↑ Reference manual section 5.4.1 page 75
  4. ↑ 4.0 4.1 Reference manual section 8.3.9 page 146
  5. ↑ Reference manual section 8.3.9 page 146
  6. ↑ Reference manual section 8.3.9 page 146
  7. ↑ Reference manual section 18.4.3 page 470
  8. ↑ Reference manual section 18.4.5 page 472
  9. ↑ Reference manual section 5.4.1 page 75
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